The present invention relates to semiconductor devices, and, more particularly, void-free, silicon filled trenches in semiconductors.
Semiconductor devices are employed in various systems for a wide variety of applications. Device fabrication typically involves a series of process steps including layering materials on a semiconductor substrate wafer, patterning and etching one or more of the material layers, doping selected layers and cleaning the wafer.
Semiconductor manufacturers continually seek new ways to improve performance, decrease cost and increase capacity of semiconductor devices. Capacity and cost improvements may be achieved by shrinking device size. For example, in the case of a dynamic random access memory (“DRAM”) chip, more memory cells can fit onto the chip by reducing the size of memory cell components such as capacitors and transistors. The size reduction results in greater memory capacity for the chip. Cost reduction is achieved through economies of scale. Unfortunately, performance can suffer when device component size is reduced. Therefore, it is a challenge to balance performance with other manufacturing constraints.
One method of shrinking device size is to vertically construct the components, either in a stack over the semiconductor substrate or within the substrate itself. One way to accomplish such vertical construction within the substrate involves forming a trench in the substrate. By way of example only, a capacitor may be fabricated within a trench. Such a capacitor is known as a “trench capacitor.”
The capacitor stores charge and includes a pair of electrodes separated by a dielectric material. The charge can represent a data value for use in a memory cell, such as a DRAM cell. While it is desirable to shrink the surface area of a trench capacitor to increase memory cell density, the trench capacitor must be able to store a sufficient amount of charge. For example, regardless of size, a trench capacitor of a DRAM cell typically requires a charge on the order of 25–30 fF (femto Farads). Therefore, it is imperative that trench capacitors be able to store sufficient charge. This may be accomplished by creating trenches which extend relatively deep into the substrate.
A conventional trench capacitor is typically formed as follows. First, a trench is etched in the substrate. The trench has sidewalls defined by surrounding portions of the substrate. Then, an outer electrode, a “buried plate,” is formed by implanting a dopant in the substrate surrounding the trench. Next, a dielectric liner, the “node dielectric,” is formed along the sidewalls, covering the outer electrode. Subsequently, an inner electrode is deposited within the trench. The inner electrode typically consists of amorphous silicon or polycrystalline silicon, and “a-Si or polysilicon” or “poly-Si”, respectively. Amorphous silicon does not have a long range crystalline structure, and a-Si or polysilicon has a semicrystalline structure. From a processing point of view, the electrode may be deposited in form of an amorphous film and, by applying a high temperature in subsequent processing, the amorphous silicon may undergo a phase transition to a poly crystalline state.
In conventional processing, the trench is formed relatively deep within the substrate. For example, a “deep trench” may extend between 4–8 μm below the substrate surface at a given stage in the fabrication process. Deep trenches are typically high aspect ratio trenches. The “aspect ratio” is the ratio of the depth of a trench compared to the width of the opening at the top of the trench. By way of example only, high aspect ratio trenches in advanced semiconductor manufacturing may have an aspect ratio of between 20:1 and 60:1 or higher.
A high aspect ratio trench adversely impacts formation of the inner electrode. This is so because of how the inner electrode is formed. The amorphous-Si (a-Si) or polycrystalline (poly-Si) inner electrode is formed by a deposition process such as chemical vapor deposition (“CVD”). For example, a low pressure CVD (LPCVD) process may be used, wherein the pressure is below 1.5 Torr. During deposition, the a-Si or poly-Si grows inward from the sidewalls. However, this process typically creates voids, gaps or seams within a central portion of the inner electrode. In particular, a V-shaped void may form in a central portion of the inner electrode, which will be described in more detail below.
FIG. 1 shows a trench 6 formed in a substrate 1. Creating a trench having a tapered top portion 7 as shown in FIG. 1 can reduce void formation, because the tapered top allows the deposition process to better access to the trench, resulting in a more complete fill. Generally, increasing the taper angle, e.g., widening the trench opening, reduces void formation. However, larger taper adversely affects the “effective” trench depth (i.e., the depth of the trench excluding the tapered portion).
Etching through the a-Si or poly-Si will typically result in exposure of the void. Typically, the void can be healed by depositing poly-Si into the void after the collar oxide is formed. However, large voids often cause problems such as poor depth control of the healing deposition process. As such, the deposition of poly-Si within long voids running substantially the depth of the trench may not sufficiently heal the defect.
Thus, new methods of formation void free trenches and a-Si or polysilicon inner electrodes are desired. The methods should minimize or eliminate void formation in filled trench structures. Improved methods of healing pre-existing voids are also desired.